Integrated circuit on high performance chip

ABSTRACT

A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

RELATED APPLICATIONS

This application claims priority from French Patent Application No.0307617 filed Jun. 24, 2003, which is incorporated by reference herein.

BACKGROUND

The present invention relates to the field of integrated circuits, andin particular to that of passive components integrated on die.

In the field of integrated circuits, there is an increasing requirement:to reduce the size taken up by the components, to reduce the fabricationcosts, and to introduce new functions.

To achieve these objectives, it is necessary to integrate collectivelyonto the same analog or digital integrated circuit die an increasingnumber of components that were previously fabricated separately. Thereare essentially three categories of such components: circuits called“active” (transistors), components called “passive” (resistors,capacitors, inductors), and, finally, micro-electro-mechanical systems(MEMS) (acoustic filters, radio-frequency switches, variablecapacitors).

Passive components and/or MEMS can be integrated independently oftransistors, but their monolithic integration with transistors is themost beneficial in terms of compactness and cost. However, thismonolithic integration causes a certain number of technologicaldifficulties.

First, the nature of the layers and the treatments necessitated by thefabrication of the passive components are not always readily compatiblewith fabrication on the active circuits. For example, there existsituations in which the production of a second material after that of afirst material in a stack on a silicon wafer necessitates the use of atemperature higher than that above which said first material is degradedunacceptably. This is the case in particular for integrating decouplingcapacitors into integrated circuits. These capacitors must store a highelectrical charge—the electrical charge is proportional to thecapacitance and to the supply voltage, so increasing the capacitanceimproves the required performance (it will be remembered that thecapacitance is proportional to the dielectric constant and to theelectrode area and inversely proportional to the thickness of thedielectric of the capacitor).

Capacitors are conventionally produced on the same wafer as transistors.To reduce production costs, it is naturally desirable to use smallcapacitors. Obtaining the required capacitances using dielectricmaterials with a dielectric constant that is very high compared to theusual materials (SiO₂, Si₃N₄, Ta₂O₅, ZrO₂ or Al₂O₃) may then beenvisaged.

There exist ferroelectric materials, belonging to the class ofperovskites, which have very high dielectric constants (relativeconstant of several hundred units). Perovskites constitute almost all ofthe materials investigated for high-capacitance capacitor applicationsin the required range of dielectric constants (see for example the paperby T. Ayguavives et al. entitled “Physical Properties of (Ba,Sr)TiO₃Thin Films used for Integrated Capacitors in Microwave Applications”,IEEE 2001). The perovskite crystalline phase is usually obtained attemperatures from 600° C. to 700° C. However, these temperatures areincompatible with the aluminum- or copper-based interconnection metal ofthe transistors. Although certain prior art low-temperature processesuse a perovskite (see for example the paper by D. Liu et al. entitled“Integrated Thin Film Capacitor Arrays”, International Conference onHigh Density Packaging and MCMs, 1999), they in fact relate to a phasein which the perovskite is not pure or is of mediocre structural ormicrostructural quality, which means that the dielectric constant isvery much lower than that of the same material when annealed at a highertemperature.

The standard methods mentioned hereinabove therefore do not reallyexploit the advantages of perovskites, because the maximum authorizedtemperature decreases progressively as and when the process steps arecarried out, and the main difficulty results from the fact that theplacement of a “hot” process material (the dielectric) occurs after thatof a “cold” process material (the interconnection metal).

There is nevertheless known in the art a method for heating thedielectric to a temperature higher than the interconnection metals canwithstand. It consists in isolating the dielectric from theinterconnection metal by means of a thermal protection layer and thenannealing the dielectric using a pulsed laser with sufficiently briefpulses for the temperature of the metal to remain lower than thetemperature of the dielectric and to remain acceptable, provided thatthermal diffusion is relatively low (see for example the paper by P. P.Donohue et al. entitled “Pulse-Extended Excimer Laser Annealing of LeadZirconate Titanate Thin Films”, proceedings of the 12th InternationalSymposium on Integrated Ferroelectrics, Aachen, Germany, March 2000,published in Integrated Ferroelectrics, vol. 31, pages 285 to 296,2000). This method is difficult to control, however, because theprotective layer remains on the wafer. The protective layer thereforecannot be very thick (it is usually less than 2 μm thick), and it mayaffect the electrical performance of the devices. The temperaturedifference between the interconnection metal and the dielectric istherefore limited; in other words, the temperature to which thedielectric may be subjected is limited. Moreover, the stack is subjectedto a high thermal gradient during this operation, which can generate asurface temperature that is too high or cause non-homogeneouscrystallization of the dielectric or deterioration of materials, such asmicrocracks, as a result of thermal expansion.

One prior art solution to this temperature problem consists in producingthe passive devices incorporating the capacitors on a silicon waferother than the substrate containing the active components and thenconnecting the two dies together by wires or by microballs (see forexample the paper by R. Heistand et al. entitled “Advances in PassiveIntegration for C/RC Arrays & Networks with Novel Thin & Thick FilmMaterials”, 36th Nordic IMAPS conference, Helsinki, 1999). These methodshave certain drawbacks, however: wires cannot be used to make shortconnections between capacitor and transistors, and microball connectionsmay be produced on top of a circuit only once; if the capacitors aremade of this material, it is no longer possible to add other functionssuch as switches or surface wave filters, for example.

To avoid these problems, the production temperature is usually limitedto about 450° C., which enables integration of the components in theusual metallizations, or above them, in integrated circuits based onaluminum or copper (see for example the paper by S. Jenei et al.entitled “High-Q Inductors and Capacitors on Si Substrate”, IEEE 2001,or the paper by Bryan C. Hendrix et al. entitled “Low-TemperatureProcess for High-Density Thin-Film Integrated Capacitors”, InternationalConference on High-Density Interconnect and Systems Packaging, 2000).Because of this temperature limit, these standard methods are greatlylimited in terms of the type of material and the dielectric constantsthat can be achieved. The required capacitance values are thereforeobtained by producing capacitors occupying a large area, which limitsthe integration possibilities and adds to the cost of the die because ofthe increased area that is occupied on the silicon wafer.

There is nevertheless known in the art a method for increasing the areaof the electrodes without increasing the lateral dimensions of the die(see the paper by F. Roozeboom et al. entitled “High-Value MOS CapacitorArrays in Ultradeep Trenches in Silicon”, published in MicroelectronicEngineering, vol. 53, pages 581 to 584, Elsevier Science 2000). Thismethod consists in exploiting the depth of the substrate to integratemetal oxide semiconductor (MOS) decoupling capacitors by excavating anarray of deep narrow trenches in the substrate: a dielectric layer andthen an electrode layer are disposed around these trenches—the otherelectrode of the array of capacitors covers the surface of thesubstrate. However, apart from the difficulty of producing uniformdielectric layers in the trenches, the use of capacitor arrays intrenches makes planar integration of passive components with activecomponents difficult.

More generally, a second difficulty arising from the monolithicintegration of passive components or MEMS with transistors is that it isnot possible to exploit the vertical dimension to improve thecharacteristics or the compactness of the passive components.

A third difficulty to which the monolithic integration of passivecomponents or MEMS with transistors gives rise is that the type ofsubstrate used for the active circuits disturbs the characteristics ofthe passive components.

For example, the substrates used for CMOS or BICMOS circuits haveconductivities of the order of 10 Ω.cm at most. The currents induced inthese substrates by the inductors or conductive lines cause high lossesand thereby reduce the quality factors of these structures (highinductance, high resonant frequency, low stray capacitance).

A first prior art solution consists in eliminating a portion of thesubstrate under the areas that are to receive the inductors andconductive lines (see for example U.S. Pat. No. 5,539,241). A secondprior art solution consists in making the substrate insulative under theareas that are to receive the inductors and conductive lines (see forexample the paper by H.-S. Kim et al. entitled “A Porous-Si-based NovelIsolation Technology for Mixed-Signal Integrated Circuits”, Symposium onVLSI Technology, 2000). A third solution is disclosed in U.S. Pat. No.6,310,387—the underlying conductive layers are structured by producing alarge number of small conductive areas in a checkerboard pattern thatare separated from each other by an insulator and are not grounded.These areas serve as shielding because, in operation, low eddy currentsare produced therein that prevent the magnetic field penetrating as faras the substrate; these areas are small enough to prevent these eddycurrents inducing in the inductors a magnetic flux opposite to therequired flux.

However, these various techniques are complex to use, may compromise therobustness of the integrated circuit and make the placement of activecomponents difficult.

Finally, a difficulty raised specifically by the monolithic integrationof MEMS with transistors is that it is necessary to add a cover toprotect the mechanical components, without interfering with theiroperation. One prior art solution consists in bonding a silicon wafer ofthe same diameter as the wafer on which the circuits have been produced(see for example the paper by H. Tilmans et al. entitled “Zero-LevelPackaging for MEMS or MST Devices: the IRS Method”, mstnews 1/00). Thistechnology is relatively costly because it is necessary to add to thecost of the supplementary substrate the cost of bonding, the cost ofthinning and the cost of local etching to obtain access to the outputelectrical contacts on the surface of the circuit, and all of this isneeded only to provide protection by means of a cover.

BRIEF SUMMARY

To solve most of the difficulties described hereinabove, a first aspectof the invention proposes a method of fabricating a die containing anintegrated circuit comprising active components and passive components,said method being distinguished in that it comprises the followingsteps: a first substrate is produced containing at least one activecomponent of said active components and a second substrate is producedcontaining “critical” components of said passive components, and the twosubstrates are bonded by layer transfer. The active components may betransistors, for example.

Passive components are said to be “critical” if their productiondirectly on the substrate containing the active circuits and themetallic interconnections would give rise to a problem; for the reasonsexplained hereinabove, this may refer to MEMS, for example, and/orhigh-quality inductors and/or capacitors whose dielectric material is aperovskite.

Certain critical passive components, such as MEMS and/or capacitors, arepreferably produced in said second substrate before said bonding of thetwo substrates.

According to the invention, a second material may in particular beproduced on a silicon substrate at a temperature higher than the maximumtemperature to which the silicon substrate may be heated because of afirst material already present on the wafer. The invention enables thisby producing the second material separately from the silicon wafer onwhich it is to end up and then integrating the second material onto thatwafer by layer transfer techniques. In the particular case of decouplingcapacitors, the invention enables the dielectric material of thecapacitor to be heated to temperatures enabling crystallization in theperovskite phase without any restriction being imposed by the underlyinginterconnection metal and without having recourse to a thermalprotection barrier between the two materials.

The method of the invention also produces conveniently a structure forprotecting the MEMS. This is because the MEMS being produced on thesurface of the second substrate that is to be transferred onto the firstsubstrate is this first substrate itself (in which an appropriate cavityhas been formed beforehand) that serves as a protective structure forthe MEMS after bonding the two substrates. This has the advantage thatit economizes on the production of a cover as in the prior art.

According to particular features of the invention, dielectric insulationtrenches intended to reduce electromagnetic interference between thevarious components of the future die are further produced during theproduction of the second substrate.

According to other particular features, non-critical passive components,such as capacitor arrays in trenches are further produced during theproduction of the second substrate.

Certain other critical passive components are preferably produced in thevicinity of the face of the second substrate opposite the bonding faceafter said bonding of the two substrates. In the case of inductors, thishas the advantage of considerably reducing the effects of the inducedcurrents (energy losses, interference suffered by the active components,etc.), even if the second substrate is conductive, since this places theinductors far from the first substrate.

To reduce further the losses caused by induced currents and to improvethe quality factors of the inductors, according to particular features,the inductors will be produced on top of inductive insulation trenchespreviously formed in the second substrate. A second aspect of theinvention also relates to different dies containing integrated circuits.

Thus, first, the invention relates to a die fabricated by any of themethods briefly described above. Second, the invention relates to a diecontaining an integrated circuit comprising active components andpassive components and consisting of a single stack of layers, said diebeing distinguished in that it includes an interface between two of saidlayers such that the portion of the die situated on one side of saidinterface contains at least one active component of said activecomponents and the other portion of the die contains “critical”components of said passive components. According to particular features,said critical passive components comprise capacitors whose dielectricmaterial is a perovskite and/or MEMS enclosed in cavities situatedinside said die.

According to particular features, the die further comprises dielectricinsulation trenches. According to other particular features, saidintegrated circuit further comprises non-critical passive componentssuch as capacitor arrays in trenches.

According to other particular features, said active components aredisposed in the vicinity of a first face of the die and said integratedcircuit further comprises inductors situated in the vicinity of the faceof the die opposite said first face. According to even more particularfeatures, said inductors are situated above inductive insulationtrenches.

According to other particular features, said active components aredisposed in the vicinity of a first face of the die which furthercomprises interconnection lines that emerge in the vicinity of the faceof the die opposite said first face. The advantages of these dies areessentially the same as those of the corresponding fabricationprocesses.

Other aspects and advantages of the invention will become apparent onreading the following detailed description of particular embodimentsgiven below by way of non-limiting example.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be better understood with reference to the followingdrawings and description. The components in the figures are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention. Moreover, in the figures, likereferenced numerals designate corresponding parts throughout thedifferent views.

FIG. 1 shows a first substrate treated by one embodiment of theinvention.

FIG. 2 shows a second substrate treated by that embodiment of theinvention.

FIG. 3 shows the assembly obtained after transfer in accordance with theinvention of said second substrate 2 onto said first substrate 1.

FIG. 4 shows the die obtained by this embodiment of the invention.

FIG. 5 is a view to a larger scale of a portion of FIG. 4.

DETAILED DESCRIPTION

FIG. 1 shows a “first” substrate 1 consisting of a wafer of silicon orany other type III-V semiconductor material. The method of the inventionbegins with the preparation of two substrates 1 and 2 in either order orsimultaneously. This first substrate 1 contains active components 3 thathave been integrated by any technique known in the art (for example theCMOS or BICMOS technique) and metal interconnections (not shown).

In this embodiment, a thick layer 4 of insulation, for example SiO₂, isdeposited and, where appropriate, etched locally (forming cavities 5) invertical alignment with any Microelectromechanical Systems (MEMS)components on the second substrate. Finally, metallization areas 9 areproduced that are subsequently connected to other portions of the die(see below).

FIG. 2 represents a wafer forming a “second” substrate 2. In thisembodiment, the second substrate 2 has been formed with: dielectricinsulating trenches 6, capacitors 7 with a very high dielectricconstant, MEMS 8, capacitor arrays 15 in trenches, and inductiveinsulation trenches 18.

The fabrication of capacitors 7 whose dielectric material is aperovskite will be described in detail. Two embodiments will bedescribed by way of example. In a first embodiment of capacitors 7 whosedielectric material is a perovskite, a second substrate 2 is made of aninsulative material, high-resistivity silicon or a semi-insulator suchas glass. The following steps are then carried out: a) a layer ofsilicon oxide SiO₂ is deposited; b) a first electrode is deposited. Thefirst electrode may consist of a plurality of layers of metallicmaterials, for example, a layer of Ti, RuO₂ or IrO₂, covered with alayer of platinum; c) using any prior art method (for example the SolGel, cathode sputtering or MOCVD method), the dielectric material isdeposited, consisting of a thin layer of a perovskite such as SrTiO₃,Pb(Zr_(x)Ti_(1-x))O₃ (known as “PZT”) or (Ba_(x)Sr_(1-x))TiO₃ (known as“BST”); d) the dielectric material is annealed at a high temperature(for example 700° C.) to obtain the perovskite phase; e) a secondelectrode is deposited, which may consist of a plurality of layers ofmetallic materials, for example a layer of platinum covered with a layerof Ti; and f) a layer of insulation, for example SiO₂, is preferablydeposited to encourage subsequent bonding (see below).

Another method of fabricating capacitors 7, whose dielectric material isa perovskite, uses as the second substrate 2 a thick layer of perovskiteproduced beforehand. In this case, the above steps a) to d) are omitted.

The method of the invention therefore produces, at the required hightemperature, capacitors having a dielectric of very high dielectricconstant without risk of damaging the active components or the metallicinterconnections of the future integrated circuit.

The MEMS components 8 may operate electromechanically orelectroacoustically, such as electromechanical switches or acousticresonators. The MEMS components 8 are produced in a manner that is knownin the art by a succession of deposition and etching operations.

The fabrication of capacitor arrays in trenches 15 is described indetail next. The capacitors have electrodes of large area (and thereforealso of high capacitance), which are implanted as described in the paperby F. Roozeboom cited above. To be more precise: a) trenches are etchedin accordance with predefined patterns and to a depth slightly greaterthan the future thickness of the substrate after thinning (see below);b) a high-quality dielectric is grown on the faces of each trench. Thisdielectric must be as thin as possible for the capacitance values of thecapacitors 15 to be as high as possible. For example, if the voltage tobe applied to the terminals of the capacitors is a few volts, athickness of dielectric from 10 nm to 50 nm is preferably grown. If thesubstrate 2 is of silicon, silicon oxide obtained by a thermal effect isadvantageously used for this purpose, possibly in combination withnitriding or deposition of silicon nitride. Dielectrics of higherpermittivity may also be used, for example Al₂O₃, HgO₂ or Ta₂O₅deposited in a manner known in the art; c) the trenches are filled witha highly conductive material to produce one of the plates of thecapacitor. Undoped polycrystalline silicon or polycrystalline siliconthat is doped in situ may be used for this purpose, for example; and d)localized etching of said highly conductive material is carried out bymasking to delimit areas on the surface of the substrate 2 and isolatethe plates of the capacitor from the remainder of the semiconductorcircuit.

A high-conductivity material (such as silicon) is preferably selectedfor the substrate 2 because the substrate will constitute one of theplates of the capacitors in trenches. The flanks of the trenches on thesubstrate side must be strongly doped to render the substratesufficiently conductive. Finally, an ohmic contact will be produced onthe substrate in order to be able to connect one electrode of thecapacitors to an electrical circuit.

Alternatively, in the case of integrated circuits that do not includeany capacitor arrays in trenches, it is instead preferable to select alow-conductivity material (such as glass) for the second substrate 2 tolimit the losses caused by induced currents generated by the inductors(see below).

By making it possible to excavate deep trenches in the second substrate2, the invention grows electrodes of large area for these capacitors andthereby, for a given substrate lateral area, considerably increases thecapacitance value compared to a standard monolithic integration method.

The inductive insulation trenches 18 are produced in accordance with theteaching of U.S. Pat. No. 6,310,387 summarized above. As alreadyexplained, these trenches 18 contribute to the production of inductorsof high quality.

Finally, metallization produces contacts on the plates of the capacitors7 of very high capacitance value, and on the MEMS 8 and connects them toeach other. Metallization areas 10 are also produced that aresubsequently connected to other portions of the die by vias formedthrough the second substrate 2 (see below). Mechanical-chemicalpolishing is preferably applied to the upper layer of the resultingwafer to impart to it a roughness encouraging layer transfer bymolecular adhesion.

FIG. 3 shows the combination obtained after bonding the second substrate2 onto the first substrate 1 by the method of the invention. The bondbetween the first substrate 1 and the second substrate 2 is preferablyobtained by molecular adhesion or polymer gluing. It is preferable toavoid using a glue layer in order not to increase the total number oflayers. However, this bond could also be produced by eutectic or anodicbonding, for example. It may be inconvenient to use soldering andbrazing here, however, because of the attendant problems, well known tothe person skilled in the art, of wettability, degassing and thermalinsulation.

Thus, in the die produced by the method of the invention, the interfaceat which the two substrates have been bonded delimits two portions ofthe die. One portion contains at least one active component of theintegrated circuit and the other portion contains the criticalcomponents of the integrated circuit.

It will be noted in particular that, in this embodiment, the alignmentbetween the MEMS 8 and the cavities 5 is respected. Thus, thefabrication method of the invention protects electromechanicalcomponents such as these MEMS 8.

At this stage, to complete the fabrication of the die of the invention,it is necessary to construct the array of interconnections forconnecting the electrodes of the capacitors and the underlying array ofinterconnections of the second substrate 2. It will be noted that here,in the context of the invention, access to buried layers is facilitated,in contrast to prior art monolithic fabrication methods, in which eachsuccessive layer may be deposited and immediately etched.

These final steps yield the die 100 shown in FIG. 4: a) The secondsubstrate 2 is thinned and polished, for example by mechanical-chemicalpolishing. As explained in patent EP0807970, it is also possible toeffect ionic implantation in a plane of the substrate 2 to createmicrocavities that weaken the substrate and allow subsequent fracture inthis plane. Thinning is continued until it penetrates into the trenchstructures 6, 15 and 18; a first substrate is produced containing atleast one active component of said active components and a secondsubstrate is produced containing “critical” components of said passivecomponents, and the two substrates are bonded by layer transfer; b) thesecond substrate 2, and then the dielectric layers in vertical alignmenttherewith are etched locally to uncover the future contacts on themetallization areas 9 and on the metallization areas 10; c) an insulator11, for example SiO₂, is deposited at low temperature to cover the freesurface of the second substrate 2; d) vias 16 (respectively 17) areproduced to connect the metallization areas 9 (respectively 10) to thefree surface of the insulator 11. In this embodiment the techniquedisclosed in the paper by M. Tomisaka et al. entitled “Electroplating CuFillings for Through-Vias for Three-Dimensional Chip Stacking”(Electronic Components and Technology Conference, 2002) is used. FIG. 5shows this interconnection between the components of the first substrate1 and the components of the second substrate 2 by means of vias. Theinsulator 11 is etched first: to produce recessed patterns and holesknown as “vias” in the insulator at predetermined locations intended todelimit future conductive lines, and to eliminate the insulator at thebottom of the vias. This etching is followed by conductive metallizationof the surface and the inside of the holes formed in the insulator. Forthis purpose, thin layers of TaN or TiN are deposited, and thiscontinuous base layer is used for electrolytic deposition of thickcopper; and e) this copper and said continuous base layer are planarizedusing techniques known in the art (for example mechanical-chemicalpolishing) until the copper and the continuous base layer are completelyeliminated from the higher areas of the insulator, so as to leave metalonly in the recessed patterns produced in the step d) in the trenches ofthe insulator and in the vertical holes. In this way, vias (16, 17) andinductors 12 on the surface with a so-called “Damascene” structure areobtained (see FIG. 5). The depth of the recesses and the thickness ofthe metal are selected to minimize the resistance of this layer.

In a different embodiment, the metallization may be effected, in amanner known in the art, by a tungsten via associated with aluminumlines or areas.

The invention greatly reduces induced current losses, because producingthese inductors 12 on the face of the second substrate 2 opposite thebonding face moves these inductors 12 away from the first substrate 1(which may be a good conductor), and away from the trenches 18 situatedunder the inductors 12 to eliminate induced currents.

The present invention is not limited to the embodiments describedhereinabove. The person skilled in the art will be able to developdiverse variants of the invention without departing from the scope ofthe appended claims. For example, there are described above embodimentsin which the etching of the various layers is effected aftertransferring the second substrate onto the first. However, it isentirely possible to effect certain etching steps on the first substrate1 and/or on the second substrate 2 before the transfer step. Also, otherelements could naturally be added to the elements constituting theembodiments described above, such as barrier layers or non-stick layers.

Any embodiment of the fabrication method of the invention comprises, asexplained above and as shown in the figures, the bonding of thesubstrates (1) and (2) by layer transfer, i.e., by adhesion of a face ofthe first substrate (1) to a face of the second substrate (2) over themajor portion of their area (known as “full wafer” adhesion).

It will be noted that the die obtained in this way is particularlyrobust, as it consists of a single stack of layers (compared to priorart devices consisting of portions joined together by soldering orbrazing joints or beads). This robustness in particular enables the safeproduction of cavities (hollow patterns, vias, etc.) in the die duringthe final fabrication stages, i.e., after bonding the two substrates. Asexplained above, inductors or interconnections (for example) maytherefore be included in the integrated circuit in a manner that isparticularly convenient. It will also be noted that, for the samereasons, the die obtained in this way is particularly compact comparedto said prior art devices.

While various embodiments of the invention have been described, it willbe apparent to those of ordinary skill in the art that many moreembodiments and implementations are possible within the scope of theinvention. Accordingly, the invention is not to be restricted except inlight of the attached claims and their equivalents.

1. A method of fabricating a die containing an integrated circuitcomprising active components and passive components, at least a part ofthe passive components comprising critical passive components, themethod comprising: producing a first substrate including at least oneactive component including heating the first substrate at a temperaturelower than a first temperature above which the first substrate isunacceptably degraded; producing a second substrate including thecritical passive components including heating the second substrate at atemperature higher than the first temperature; bonding the first andsecond substrates, wherein the bonding comprises performing a layertransfer; and after bonding of the first and second substrates,producing at least one interconnection line between the components ofthe first and second substrates, the interconnection line passingthrough the second substrate.
 2. A method according to claim 1, whereinthe at least one active component comprises transistors.
 3. A methodaccording to claim 1, wherein the critical passive components compriseat least one capacitor and at least one microelectromechanical system(MEMS).
 4. A method according to claim 1 wherein the critical passivecomponents comprise at least one capacitor or at least onemicroelectromechanical system (MEMS).
 5. A method according to claim 3,wherein a dielectric material of the at least one capacitor comprises aperovskite.
 6. A method according to claim 1, wherein producing thesecond substrate comprises producing an electrically conductivematerial.
 7. A method according to claim 1, wherein producing the secondsubstrate comprises producing a dielectric material.
 8. A methodaccording to claim 7, wherein producing the second substrate comprisesproducing perovskite.
 9. A method according to claim 1 furthercomprising producing dielectric insulation trenches in the secondsubstrate during the production of the second substrate.
 10. A methodaccording to claim 1 further comprising producing at least onenon-critical passive component during the production of the secondsubstrate.
 11. A method according to claim 10, wherein producing thenon-critical passive component comprises producing a capacitor intrenches.
 12. A method according to claim 9 further comprising producingat least one inductor in the vicinity of a face of the second substrateopposite a bonding face after the bonding of the two substrates.
 13. Amethod according to claim 12 further comprising producing the at leastone inductor on the dielectric insulation trenches.
 14. A die fabricatedby a method according to claim
 1. 15. A die made of a single stack oflayers, containing an integrated circuit comprising active componentsproduced at a temperature lower than a first temperature above which theactive components are unacceptably degraded and comprising passivecomponents, wherein at least a part of the passive components comprisingcritical passive components produced at a temperature higher than thefirst temperature above which the active components are unacceptablydegraded, wherein the die comprises an interface between two of thelayers such that a first portion of the die situated on one side of theinterface includes the active component and a second portion of the diesituated on the other side of the interface includes the criticalpassive components produced at the temperature higher than the firsttemperature, wherein the die comprises at least one interconnection linebetween the components of the first and second portions, theinterconnection line passing through the second portion of the die. 16.A die according to claim 15 wherein the critical passive componentscomprise at least one capacitor and at least one MEMS enclosed in acavity situated inside the die.
 17. A die according to claim 16, whereinthe at least one capacitor comprises a dielectric material comprisingperovskite.
 18. A die according to claim 15, wherein the die furthercomprises dielectric insulation trenches.
 19. A die according to claim15, wherein the integrated circuit further comprises at least onenon-critical passive component.
 20. A die according to claim 19 whereinthe non-critical passive component comprises a capacitor in trenches.21. A die according to claim 15, wherein the active components aredisposed in the vicinity of a first face of the die and wherein theintegrated circuit further comprises at least one inductor situated in avicinity of the face of the die opposite the first face.
 22. A dieaccording to claim 21, wherein the at least one inductor is situated oninductive insulation trenches.
 23. A die according to any one of claim15, wherein the active components are disposed in a vicinity of a firstface of the die and the die further comprises at least oneinterconnection line that emerges in the vicinity of the face of the dieopposite the first face.
 24. A die according to any one of claim 19wherein the active components are disposed in a vicinity of a first faceof the die and the die further comprises at least one interconnectionline that emerges in the vicinity of the face of the die opposite thefirst face.
 25. A method according to claim 13, wherein the at least oneinductor and at least one of the interconnection lines are producedduring a same process step.
 26. The method according to claim 1, whereinthe first temperature is about 450° C.
 27. The method according to claim1, wherein producing the first substrate comprises producing a substrateincluding all of the active components of the integrated circuit, andwherein producing the second substrate comprises producing a substrateincluding only passive components.
 28. The method according to claim 1,wherein producing the first substrate further comprises producing the atleast one active component comprising an interconnect metal thatunacceptably degraded at a temperature above the first temperature.